The Design and Implementation of Low-power Cmos Radio Receivers a Dissertation Submitted to the Department of Electrical Engineering and the Committee on Graduate Studies of Stanford University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

A S CMOS technologies continue to enjoy the bene ts of aggressive scaling, they become increasingly attractive for use in wireless receivers. Peak device fT 's on the order of 15GHz are available with 0.5 m CMOS devices, making possible CMOS implementations of radio receivers in the 1-2GHz frequency range. One wireless system in this range that is particularly amenable to integration is a Global Positioning System (GPS), whose signals are at 1.57542GHz. This dissertation explores architectural and design techniques for CMOS wireless receivers through the vehicle of the GPS system. This system comprises 24 satellites in low earth orbit that continuously broadcast their position and local time. Through satellite range measurements, a receiver can determine its absolute position and time anywhere on Earth, as long as four satellites are within view. Portable, consumer GPS applications require receivers that are compact, cheap and low-power. Examples of such applications include automotive or maritime navigation, intelligent hand-o algorithms in cellular telephony, and cellular emergency (911) services, to name a few. To enable a cheap, low-power CMOS GPS solution, this work develops a receiver architecture that lends itself to complete integration. To implement this architecture, two major foci are the design of low-noise ampli ers (LNAs) and power-e cient active lters in CMOS technologies. Theoretical investigations of the LNA problem illustrate important de ciencies of present-day CMOS models that frustrate the design task. Methods for circumventing those de ciencies are presented, leading ultimately to a power-constrained optimization of LNA noise performance. This improved theoretical basis enables iii the realization of a 2.4dB noise gure, di erential LNA with only 12mW power consumption in a 0.5 m CMOS technology. Another focus is on the power-e cient implementation of wide dynamic range active lters. In such lters, the design of the transconductor element is critical, and techniques for evaluating transconductor architectures are presented. An application of these ideas to the GPS receiver problem results in a 10mW, 60dB peak spuriousfree dynamic range (SFDR) active lter with 3.5MHz bandwidth. These advances enable the realization of a 115mW CMOS GPS receiver that includes the complete RF and analog signal path, frequency synthesizer and A/D converters. The receiver achieves a level of performance that compares favorably with existing commercial solutions in more expensive bipolar and BiCMOS technologies, delivering an overall noise gure of 2.8dB and a peak SFDR of 56dB while occupying only 11.2mm in a 0.5 m CMOS technology.